Description of the Work Packages

Work package 1 WP1 is developing of a highly efficient telecom power converter (rectifier) based on GaN power transistors. The converter will operate at higher frequencies (target 300~500kHz). This facilitates the increase of power density and the reduction of system weight by reducing the size of the passive components and heat sinks. Furthermore, due the reduced switching losses a more reliable system is anticipated. In order to evaluate the benefit of the developed GaN power devices in real system environment, these devices will be benchmarked against state-of-the-art solutions with silicon super junction MOSFETs and silicon carbide diodes.
Work package 2 GaN devices will have drastically reduced chip sizes for the same on-state resistance compared to state-of-the-art silicon power devices. We expect up to a factor of ten in chip shrink. The corresponding reduction of power losses by the higher switching performance of GaN devices will not fully compensate for the effect of chip size reduction. Thus, taking full advantage of the beneficial GaN properties the power density will be even higher than that of previous silicon based devices. This work package will address the important task of removing the locally generated heat from the active zone of the GaN device most effectively. GaN-on-Si has the inherent disadvantage of higher thermal resistance vs. GaN-on-SiC due to the worse thermal properties of the silicon substrate vs. silicon carbide. This disadvantage will be tackled by thin wafer technology and a drastic reduction of the bond line thickness by advanced die attach methods. Additionally different front side metal concepts will be evaluated for further equilibration of possible thermal hot spots. GaN power devices with their improved switching performance generally allow for higher switching frequencies, which is highly welcome to reduce the size of passive components in the application. On the other side this will only be possible by lowering the corresponding parasitic passive components of the package being used. Therefore this work package includes the development of an appropriate 600V capable GaN adapted power package with very low inductances.
Work package 3 For the development of modern semiconductor devices it has become indispensable in the past decades to assess device concepts by numerical simulations of their physical and electrical properties already in a very early phase of development. This methodology is described by the term TCAD (Technology Computer Aided Design). In the past there has been tremendous progress in the quality of process and device simulation for silicon based devices. This level of maturity still has to be reached for simulation of GaN hetero structures. This work package is aimed at setting up an appropriate TCAD environment for GaN devices including calibration to experimental device data. Target is to allow physical device simulation of static and dynamic device parameters and therefore to allow comparison of different device concepts regarding performance. It is furthermore planned to extract simplified PSpice models from TCAD and experimental characterization data including package parasitic components. This allows to perform circuit simulations to assess the behavior of different device concepts in the application. Last but not least also the static and transient thermal and thermo-mechanical behavior of the devices in the package will be modeled.
Work package 4 Main objective of work package 4 is the development of normally-off GaN power FETs with 750 V breakdown strength and 20 mW on-state resistance for 500 kHz switching frequency. The device technology will be based on AlGaN/GaN HEMTs with a p-type GaN gate for the normally-off characteristic. Silicon will be used as substrate and a technology to enable a drain- or source-down topology of the devices will be developed. This will allow the flexible use of the devices as either low-side or high-side switch in a converter module. The device design will be optimized for high-temperature operation with 225°C channel temperature. The vertical and lateral thermal heat flow will be measured for devices processed on Si and SiC substrates to determine the difference in device thermal impedance for the two substrates and their required epitaxial transition layers. On-wafer robustness and reliability measurements will be performed for both, fast iterative improvement of the device technology and for benchmarking the GaN-on-Si technology against GaN-on-SiC devices. A process module transfer from Ferdinand-Braun-Institute to Infineon is planned and the GaN-on-Si device production capability under high-volume industrial environment will be checked at Infineon. This includes the development of specific processing modules and the use of 8” GaN-on-Si wafers from EpiGaN. Explorative normally-off device technologies developed at Vienna University and Slovak Academy of Sciences will be processed on the 3” or 4” line of Ferdiand-Braun-Institute to check for the principal process transfer ability.
Work package 5 Work package 5 is mainly focussed on the development of suitable AlGaN/GaN epitaxial layers on silicon for normally-off high power switching transistors. Effort will be spent to develop very high voltage buffers on large wafer diameters and solutions for e-mode operation. The epitaxial layers developed and fabricated in the frame of this work package will serve as the baseline for the device developments in the work packages 4 and 7. In parallel, an activity focussing on epitaxy on SiC and sapphire substrates will allow us to benchmark the GaN-on-Si technology. Another activity concerns the development of explorative structures in close collaboration with the university partners. Furthermore, in cooperation with Aixtron, this work package is also strongly linked to WP6 where a high volume concept of GaN-on Si manufacturing will be elaborated.
Work package 6 The objective of WP6 is to consider the possibilities to upgrade the MOCVD production capacity and efficiency especially with respect to HipoSwitch device structures. The WP is divided into two tasks. Within task 6.1 a 200 mm GaN on Si technology will be developed and task 6.2 is devoted to the elaboration of possibilities for high throughput, large area productions equipment for device structures developed in HipoSwitch. A critical advantage of GaN-on-Si technology over GaN-on-SiC or sapphire is the possibility to use larger wafer diameter and thus reduce the device costs. But the issues of stress within the wafers lead to higher values of the bow of the wafers and thus to more severe problems for wafers to enter an industrial process line. Nevertheless a first successful demo has been performed in 2009 by AIXTRON and the founders of EpiGaN at IMEC. However, no real power device structure has ever been demonstrated on 200 mm wafers to our best knowledge. WP6 will focus on the reduction of bow and the optimisation of high quality GaN-on-Si device wafers. In-situ monitoring techniques will be implemented to allow tracking of the wafer quality over the complete 200 mm wafer diameter and will be further developed to allow for an enhanced process control. 200 mm demonstration wafers will be delivered to Infineon for device demonstration purpose. Increasing the wafer size to 200 mm requires the adaptation and optimization of the MOCVD equipment. The key components of the reactor have to be redesigned as regards e.g. the susceptor, the heat management system and the gas inlet. All this components significantly influence the homogeneity of the deposition and therefore the wafer yield, a key factor for the later production potential. New reactor hardware will be tested in the MOCVD reactor at EpiGaN. In close collaboration between AIXTRON and EpiGaN the process results will be analysed regarding further reactor optimization potential to increased process efficiency, yield and wafer throughput. The equipment development as well as the process development will be assisted by numerical simulations.
Work package 7 The main goal of this work package is to provide feedback information to the processing work packages (WP3-GaN device development and processing and WP7- Explorative technologies) in order to allow the optimization of the fabrication process at each level. The secondary goals of this work package will be: • Set-up a new measurements system to test the devices in real switching operation • Carry out a full electrical and thermal characterisation of the developed devices • Experimental analysis of self-heating effects and breakdown phenomena • Identify technological aspects for further device improvement • Provide understanding of critical device operation conditions • Dynamic thermal and electric field mapping using optical techniques • Detection of potential reliability issues in an early stage of the project • Get a sound understanding of potential degradation mechanisms • Trigger corrective actions in processing and design iterations • Statistical lifetime data for system life time evaluations and predictions The analysis will be based on an extensive electrical, optical and thermal characterisation of GaN-based devices at different ambient temperatures and after the submission to stress tests. The data on the device characterisation as well as those obtained after device degradation of the stressed samples (together with the hypothesis on the degradation mechanisms) will be provided to device manufacturers as a feedback on the quality of the growth and fabrication process. Lifetime evalua-tion and forecasting will be possible thanks to the extensive analysis of the degradation of power GaN-HEMTs submitted to stress under different current/temperature levels.
Work package 8 This work package is dedicated to explorative studies towards the development of new normally-off (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs) on Si substrate. Several strategies and designs are tested and evaluated by the partners in this work package, like the use of gate oxides (MOSHEMTs) and cap layers (doped and undoped GaN). Therefore, it is important to master the processing of the devices with respect to all involved materials and fabrication steps: · Selective etching of GaN on AlGaN (cap recess) · Rapid thermal annealing (RTA) of the Ohmic contacts with regard to free AlGaN surface · Deposition of gate oxides by atomic layer deposition (ALD) and characterization of the dielectric oxide layers · Passivation of the devices Furthermore, first characterizations of new devices are performed within the scope of this work package. This contains both DC and pulsed measurements of the HEMTs.Following reliability studies will be performed in WP7.